Research On Model And New Structures For Lateral Superjunction Device

Power integrated circuit requires power device to have the following features: high power, high speed, low loss and facility integration, lateral power device as the key device in power integrated circuit has became one of the hot points in power device research filed. The lateral super junction(SJ) device is a new type of lateral power devices which has great potential for development. Super junction technology makes the constraint relation between Ron and BV of vertical MOSFET devices improved form 2.5th power to 1.3th power which improves the trade-off between on-resistance(Ron) and BV. SJ technology applied in lateral double-diffused MOSFET(LDMOS) is expected to further reduce the power loss. However, for the super junction LDMOS(SJ-LDMOS), the acceptor ionization negative charges in the substrate depletion region break the charge balance between the N-type pillars and P-type pillars, resulting in the obvious neutral regions in the P-type pillars, which is called “substrate-assisted depletion effect”. It reduces BV sharply. Many scholars proposed a series of new device structures to suppress substrate-assisted depletion effect, and my group also recently proposed equivalent substrate model for lateral SJ device, revealing the essence of substrate-assisted depletion effect. These structures mostly based on the principle of charge compensation still need to be improved.In this Dissertation, based on the above research, a charge compensation model and a drift region thickness variation model for lateral SJ device are proposed. According to them, two categories of new lateral SJ device structures segmented and N-type buried layer are presented, which improve the BV and reduce the specific on-resistance(Ron,sp) of lateral SJ device. The main innovative points are listed as following:1. Charge compensation model for lateral super junction device is proposed. From the analysis of BV of lateral SJ device, three basic charge compensation ways and their charge balance conditions are obtained. Based on the solution of 2-D Poisson equation in the drift region and the components of on-resistance, the analytic expression of the surface electric field and Ron,sp for charge compensation structure is denoted. Moreover, by comparing the advantages and disadvantages of three charge compensation ways, the concept of mix compensation is proposed to optimize the design of lateral SJ device.2. Lateral segmented SJ device structure is proposed. Based on the above model, the design idea for using the variation in effective concentration of the drift region to optimize the surface electric distribution is obtained, designing three new devices:(1) Surface segmented SJ layer LDMOS. The unbalance design SJ layer provides a low on-resistance path and increases the doping concentration of drift region, resulting in a decrease of Ron,sp. The variation in the doping concentration of the P pillar modulates the surface electric field distribution, resulting in an improved BV. Moreover, the device is compatible with standard CMOS process. Experimental results indicate that the device exhibits a BV of 800 V, a Ron,sp of 207m?·cm2 and a power figure of merit(FOM, FOM=BV2/Ron,sp) of 3.1MW·cm-2 in the leading level when the drift region length is 70μm and pillar width is 2μm.(2) Bulk segmented SJ layer LDMOS. The unbalance design SJ layer is imbedded in the drift region, which further increases the doping concentration of drift region, while ensuring the withstand voltage of the device. Simulation results indicate that the device exhibits a BV of 300 V and a Ron,sp of 8.08m?·cm2 when the drift region length is 15μm and an aspect ratio of pillar height to width is 1μm/2μm. The BV is improved by 35% and the Ron,sp is reduced by 60% compared with those of the conventional RESURF LDMOS.(3) Segmented SJ-LDMOS. The P-type pillar divided into two parts with different doping concentration suppresses the charge imbalance and optimizes the surface electric field distribution, resulting in an improved BV. Moreover, the device is compatible with the conventional SJ-LDMOS process. Simulation results indicate that the device exhibits a BV of 300 V and a Ron,sp of 8.2m?·cm2 when the drift region length is 15μm and an aspect ratio of pillar height to width is 4μm/1μm. The BV is improved by 200% compared with that of the conventional SJ-LDMOS at the same Ron,sp.3. Drift region thickness variation model for lateral super junction device and N-type buried layer buffer SJ-LDMOS are proposed. The model is based on design idea of variation in the drift region thickness to optimize surface electric field distribution. By the solution of 2-D Poisson equation in the drift region and analysis of Ron,sp, the analytic expressions of the surface electric field and Ron,sp are obtained. According to this model, the N-type buried layer buffer SJ-LDMOS is proposed. The N-type buffer layer decreases the aspect ratio of pillar height to width and reduces the process difficulty. Because the substrate-assisted depletion effect is the most serious at the drain, the N-type buried layer closed to the drain further suppresses the charge imbalance by charge compensation. Moreover, the N-type buried layer changes the thickness and the effective concentration of the drift region to strengthen the electric field modulation effect. Simulation results indicate that the average value of the surface lateral electric field reaches 23V/μm which close to value of the idea critical electric field in silicon, resulting in a BV of 350 V and a Ron,sp of 21m?·cm2.