Model And Experimental Study Of Specific On-Resistance Of Lateral SOI Semi-Superjunction Devices

The SOI Smart Power IC?SPIC?,because of its SOI material dielectric layer,can achieve higher integration,smaller parasitic effects,and lower power consumption than silicon-based chips.It has been widely used in the power semiconductor device market.Therefore,it is of great significance to study the SOI lateral power device as the core device of the SOI SPIC chip.In practical applications,it is hoped that it has a low specific on-resistance in the on-state and a high reverse withstand voltage in the off-state.Therefore,superjunction?SJ?technology is introduced to alleviate the contradiction between the specific on-resistance and the withstand voltage.The lateral superjunction device has a substrate assisted depletion effect,so scholars have proposed an equivalent substrate model?ES Model?.The introduction of a charge compensation layer?CCL?has significantly improved the device's withstand voltage.However,the specific on-resistance R_on,sp of lateral super-junction devices based on the ES model has not been investigated in theory and experiments.This article aims to solve this problem.Its main work and innovation are as follows:Firstly,based on the equivalent substrate model and the ideal substrate conditions,the SOI lateral device substrate is optimized and designed.The structure satisfies ideal substrate conditions by linearly doping the drift region,and simulations verify that the substrate-assisted depletion effect can be completely suppressed,and the device withstand voltage is effectively guaranteed.Secondly,the working principle of the pressure-resistant layer of the vertical semi-superjunction device is introduced into the SOI-based lateral super-junction device.The method of optimizing the lowest specific on-resistance is studied,and the physical concept of normalized current-carrying capacity?_C is proposed for the first time.The normalized current carrying capacity?_C is used to measure the change in the current-carrying capability?CC?before and after the super-junction is introduced.The theoretical calculation shows the optimal superjunction length under the condition of normalized current-carrying capacity?_C=1.The semi-SJ LDMOS?semi-Superjunction LDMOS?has the lowest specific on-resistance under simulations.Finally,a tape-out experiment was performed on the SOI-based semi-SJ LDMOS based on the normalized current-carrying capacity,which verified the accuracy of its minimum specific on-resistance R_on,spn,sp and withstand voltage.Experiments have shown that the super-junction length corresponding to the normalized current-carrying capacity?_C=1 enables the device to obtain the lowest specific on-resistance.The experimental results show that the semi-SJ LDMOS achieves a specific on-resistance of 25.5 m?·cm²under a breakdown voltage of 464.3V,which is 37.7%lower than that of the triple RESURF device at the same breakdown voltage.