| Design of ESD protection circuits has gained much more importance as deep submicron processes pose new problems for chip protection. However, unlike core circuit design, there is almost no CAD tools to help ESD engineers to overcome these challenges.; This thesis provides an arbitrary device extractor for non-Manhattan geometry iLEX and an ESD design rule checker ESDRC.; iLEX utilizes edge-pair based scanline processing to achieve time efficiency and space efficiency. It extracts parasitic devices as well as intentional devices, vertical devices as well as horizontal devices. When coupled with iETSIM, a circuit-level ESD simulator, it can help ESD engineers identify ESD weak points before tape-out.; ESD design rule checking is different from the conventional design rule checking in that not only different rules have to be applied for different components in the ESD protection circuit, but also style of layout is of utmost importance to ensure uniform current distribution during ESD events. ESDRC first employs iLEX to extract the netlist from layout and identify the functionality of each layout object through LVS of the extracted netlist and the schematic. Specific ESD design rules are then checked for each layout object identified. |
