Investigation Of I/O Circuits And On-Chip ESD Protection For Typical Integrated Circuits Process

In this dissertation, I/O circuits and On-Chip ESD protection design, including I/O circuits design, ESD protection scheme construct, and full-chip ESD protection design, are investigated for typical processes. Based on knowing of I/O circuits'standard and principle of diode, MOSFET, and SCR, I/O circuits and ESD protection schemes are designed for High-Voltage 0.5um Bipolar-CMOS-DMOS (BCD) process,0.18um CMOS process, and 65nm CMOS Logic process. Performances of ESD protection schemes are evaluated by Transmission-Line-Pulsing system (TLP). Some of novel and practical results are achieved. A novel full-chip ESD protection scheme is also proposed. Related contents and conclusions as follows:Ⅰ. Several function modules of universal digital I/O, in this work, are designed and verified based in 0.18um CMOS process. A 5V high-tolerant universal I/O circuit is also constructed successfully by 3.3V device. Problems of leakage and the gate-oxide reliability of universal digital I/O eliminate owing to the introduction of voltage detection and control circuits for the gate and N_well of upside output driver transistor.Ⅱ. ESD protection performances, both of dual-diode protection scheme and primary, secondary dual-diode protection scheme, are investigated for 0.5um BCD process. Test results show the parasitic resistance of power metal bus has serious influences and narrows corresponding ESD design window, consequently the core circuits fails earlier. So an ESD design rule, limiting minimum width of power bus and maximum space between I/O pin and power pin, must be developed to improve the performance of dual-diode protection scheme. The test results also show the primary, secondary dual-diode protection scheme has a higher performance than the dual-diode protection scheme against fast ESD stress (such as CDM stress).Ⅲ. The effects of parallel metal routing, across metal routing and width per finger on GGNMOS ESD performance are investigated based on 0.5um BCD process. Test results show the failure current increases as the width per finger decreases for a given width of GGNMOS. The GGNMOS employed parallel metal routing scheme does not prone to arise current accumulation effect and the current in multi-finger GGNMOS can distribute uniformly. Consequently, the parallel metal routing scheme general has a higher failure current than across metal routing scheme for multi-finger GGNMOS devices.IV. ESD protection performances of gate-direct-power complementary MOSFET (GDPCMOS) and gate-coupled complementary MOSFET (GCCMOS) are investigated based on 0.5um BCD process. Test results show the gate-coupled technique can reduce the snapback voltage for MOSFET but the failure current also reduces owing to the gate over-driver effects. Besides, the failure current has something to do with the value of coupled resistance. However, the new proposed power-clamp-assisted complementary MOSFET (PCACMOS) can help to eliminate the gate over-driver effects and consequently improve the figure of merits (FOM) of MOSFET about 13.3% because of the substrate-triggered mechanism.Ⅴ. A novel capacitance-coupling complementary SCR (CCCSCR), modified from traditional complementary SCR (CSCR), is proposed and verified for 0.5um BCD process. Compared with traditional complementary SCR, the new proposed CCCSCR has a lower trigger voltage, and the trigger voltage of CCCSCR modulated by tuning the value of coupling capacitance. The new proposed CCCSCR can achieve all mode ESD stress protection, including IO-VDD,10-VSS and VDD-VSS, by effective layout placement.Ⅵ. A new connection modified complementary SCR is proposed to reduce the area of traditional complementary SCR while the ESD protection performance keeps the same. Then the ESD protection figure of merits (FOM) is improved owing to the area reduction for connection modified complementary SCR.Ⅶ. A novel gate-suppression technique is proposed in 0.5um BCD process. The suppression element in gate-suppression technique made as a buffer during ESD stress. Compared with traditional source-pump technique, the new proposed gate-suppression technique can improve the immunity of core-device against fast ESD stress (e.g. CDM stress) about 100 percent.Ⅷ. A novel capacitance coupling triggered SCR (CCTSCR) for on-chip low-voltage ESD protection application is proposed and verified in 65nm logic CMOS process. The trigger voltage of CCTSCR is adjusted by coupling capacitance, and a low trigger voltage 2.15V can be achieved through increasing the coupling capacitance. Test results show the new proposed CCTSCR can protect the 1.2V core device effectively while a lower leakage current can be achieved both in room temperature (25℃) and high temperature (125℃).Ⅹ. A cascade complementary dual-direction SCR is proposed for high-voltage ESD protection application, and corresponding trigger voltage is tuned by coupling capacitance. Compared with traditional high-voltage ESD protection element, including gate-grounded NLDMOS, gate-driver NLDSCR, substrate-triggered NLDSCR, cascade FOD device and cascade LVTSCR, the new proposed cascade complementary dual-direction SCR has the highest FOM.Ⅺ. Novel input/output ESD switch and power ESD switch are proposed to against ESD stress, and a full-chip ESD protection scheme is also constructed by above two ESD switches. Spectre simulation results show above ESD switches can turn off during ESD stress and prevent the ESD current from flowing to core circuits. It has a weakening and buffer effects during subjected to ESD stress, so the core circuits protected more effectively.