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Design And Realization Of 10GHz VCO In CMOS Process

Posted on:2016-02-12Degree:MasterType:Thesis
Country:ChinaCandidate:J YuFull Text:PDF
GTID:2308330461463134Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Voltage-controlled oscillator(VCO), as a key block of the phase-locked loop(PLL), is now widely used in communication equipments such as mobile phones and navigation terminals. Its performance parameters in terms of power consumption, phase noise and tuning range have great effect on the performance of the whole wireless communication systems. VCO is integrated in radio frequency integrated circuits(RFIC) with the explosive growth of the wireless communication technique and the advance in microelectronics technology. CMOS RFIC is regarded as the main development trend of RFIC for its low power consumption, low cost and the mature technology. Recently, it is a real challenge in the RFIC to design a high performance VCO using CMOS processes for smaller size, lower power dissipation, lower cost and higher frequency.Firstly, the history and current research situation of VCO are introduced in the paper. The basic theory and design methods are analyzed. Based on the definition of phase noise, three main phase noise models are investigated in detail and the characteristic of phase noise in different frequency regions can be explained successfully, several optimization methods of phase noise is summarized and contrasted. Finally, a low phase noise and high linearity gain LC VCO is proposed. A varactor array is adopted to improve the linearity of tuning gain. Several methods such as the optimization of noise in tail current source and large capacitor filter technology are employed to achieve good phase noise.The proposed circuit design, layout design, parasitic parameters extraction and simulation have been implemented in Cadence EDA tools with TSMC 0.18um CMOS technology. The simulation results show that the tuning range of the VCO is 9.79-10.61 GHz and the tuning gain of the 8 sub-bands varies from 128MHz/V to 170MHz/V. The circuit draws 6.2mA current from a 1.8V supply. The phase noise is-91.9dBc/Hz at 100KHz offset and-113.8dBc/Hz at 1MHz offset from 10.2GHz carrier frequency.
Keywords/Search Tags:CMOS VCO, PLL, low phase noise, noise filtering, high linearity gain
PDF Full Text Request
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