| The phase locked loop (PLL) based frequency synthesizer is an important component in wireless transceivers to provide precise and fine-tunable local oscillation frequencies. Spectrum and timing specifications of various wireless standards impose stringent requirements on frequency synthesizer performance. The necessity of monolithic integration makes frequency synthesizer design even more challenging because it involves both high frequency building blocks, such as VCO and prescaler, as well as low frequency filters and large amount of digital circuitry. Moreover, as multistandard frequency synthesizers are required for smooth migration and backward compatibility in the wireless standard evolution, hardware sharing and design reuse issues become critical for highly efficient design with fast time-to-market and first silicon success.; In this dissertation, a top-down design and bottom-up verification flow is developed targeting the difficulties in the SPICE simulation of frequency synthesizers. The mixed-mode simulation methodology with the proposed switch macromodels and the VerilogA macromodels provides much faster speed and nearly the same accuracy compared with its all-transistor counterpart.; An example of multistandard frequency synthesizers is studied, designed and implemented for GSM and WCDMA modes. The hardware sharing issues are discussed in the proposed system architecture that makes the PFD, charge pump, loop filter, integer frequency divider and VCO all shared between the two modes, which is 70% of the entire synthesizer in term of die area. This is accomplished by applying fractional frequency synthesis to the GSM mode and integer frequency synthesis to the WCDMA mode. A high-speed low power dual modulus prescaler is also proposed to operate up to 2.1GHz at 3.3V supply voltage with 11.6mW power consumption in 0.5μm CMOS.; For PLL frequency synthesizers, the loop bandwidth involves design tradeoffs between the lock time and spur level. The adaptive PLL has provided an excellent solution to this problem. In the conventional adaptive PLL, however, the loop bandwidth enhancement in the speed-up mode is constrained to approximately 1/10 of the reference frequency for stability considerations. A novel adaptation scheme is proposed that enables extended loop bandwidth enhancement by adaptively controlling the reference frequency and other loop parameters. In addition, the adjustable and programmable loop parameters in the adaptive PLL, such as the loop bandwidth, charge pump current and reference frequency, make it feasible to maximize hardware sharing in multistandard frequency synthesizers. The proposed adaptive frequency synthesizer is designed and implemented in 0.5μm CMOS at 450MHz frequency range. In the speed-up mode, the loop bandwidth is enhanced by 16 times, resulting in a fast settling time of 260μs to within 20kHz for a 72MHz frequency step. |
