High-speed MMDS transceiver implementation with GPS clock synchronization

This thesis presents the first phase in the hardware implementation of a high-speed transceiver to be used in a Multi-channel Multi-point Distribution Services (MMDS) system. Based on standard specifications, various building blocks were implemented using FPGA prototypes. Among the blocks, the forward error correction for data integrity protection is the most complicated and expensive to implement. This block includes the Reed-Solomon (RS) codec and byte interleaving to correct both random and burst errors caused by the channel. The high-speed RS decoder was designed using highly efficient algorithms and low latency VLSI circuits which are used to implement arithmetic in the Galois field GF(28). Results show a data rate of 80 Mbs was obtained using FPGA prototypes. A data rate of 200 Mbs should be achieved when ASICs are developed using the synthesizable Verilog code that was developed for this thesis.; In addition to a high bit rate, the MMDS system also requires robust synchronization in order to transmit a high-speed data stream and to ensure data integrity. Timing and synchronization are critical in system design. These include both clock and frame synchronization. In the absence of SONET and SDH, a precise frequency from the GPS is used for the system reference clock instead of crystal oscillators. This frequency and time have very high accuracy that is directly and continuously traceable to the Coordinates Universal Time. A reference 10 MHz clock with TTL output levels was generated from a GPS clock. This clock was used in the development of the high-speed MMDS system and the clock is proposed to be used for system clock synchronization. Precision timing combined with a word synchronization scheme makes the MMDS system simple, robust, low cost and reliable.