Self-restored current-mode CMOS multiple-valued logic design and synthesis

This thesis presents a self-restored current-mode CMOS multiple-valued logic (MVL) design architecture which consists of an input block, a control block, and an output block. An r-valued logic function to be implemented by this architecture is expressed with an arithmetic sum of r − 1 disjoint binary subfunctions. The subfunctions are in a sum-of-products (SOPS) form, where a product term (PT) consists of multiple binary and operations on up-literal operators and the sum is a binary or operation. For a given MVL function, the input block implements the up-literal operators. The control block implements the r − 1 binary subfunctions. The signals from the control block turn on/off switches in the output block to generate the desired output signals directly from current sources.; The average transistor count of 2-variable 4-valued logic functions is 1.1 to 2.5 times smaller than that of other operator-based MVL designs without sacrificing speed and power. With the NMOS variant, the estimated transistor count of 2-variable 4-valued functions is comparable to that of equivalent binary logic circuits. The circuit size of the self-restored MVL designs can be further reduced by using the sum and diff operations. Some of the example logic functions show that the average transistors count can be reduced by as much as 50% as compared to the self-restored MVL designs without using the arithmetic operators.; The self-restored MVL architecture allows MVL synthesis using a binary logic synthesizer. A computer program was developed to work together with a binary logic synthesizer to generate an area-optimized circuit for a given MVL function according to the self-restored MVL design architecture. An additional computer program was also designed to automatically derive equivalent binary logic circuits for a given MVL function for comparison purposes.; This thesis also proposes a new VHDL library for high-level simulation of current-mode CMOS logic designs supporting faster verification of synthesized results without using a time-consuming circuit simulator. The library has basic MVL circuit elements, complex MVL operators as well as standard binary logic gates. A bus resolution function working cooperatively with the basic MVL entities allows MVL logic levels in individual connections to be displayed.