| This thesis begins with a discussion of clocked storage elements in general, and then narrows its focus to current-mode logic (CML) after simulation results for high speed applications have been considered. Emphasis is given to the more important circuit characteristics, especially those involving timing and metastable behavior.; The results of simulations involving high-speed devices using a number of established technologies decisively militated for the CMOS current-mode logic model, at least in the case of 0.18mum CMOS design rules.; A consideration of past efforts to improve the characteristics of CML devices results in a new 'clock feedback' CML (CFCML) latch being proposed.; An explicit circuit example to demonstrate the advantages of CFCML was needed. What was selected for this purpose was the high-frequency static frequency divider, two versions of which were designed and fabricated (TSMC 0.18mum CMOS technology). It was found that a 10GHz CFCML divider requires only 350muA current from a 1.2V supply (0.42 mW) and has an input sensitivity of 10mV at 9.4GHz. The performances of two different implementations of a 3/4 dual-modulus prescaler, one involving an external modulus control block, and the other an embedded one, are compared. A model for an asynchronous divider architecture which offers savings of 20% for each of power consumption and chip area is reported. |
