A16-bit1GSPS MOS Current Mode Logic D/A Converter Design

Demand for high-speed and high-resolution digital–analog converters (DACs)continues to grow every year, driven primarily by strong growth in the markets forwired communication systems such as wireless transmitters, direct digital synthesis,xDSL, mobile cellular networks. Such applications require DACs to be capable ofhandling data at speeds of several tens or hundreds of MS/s, with data word resolutionon the order of10–16bits. To meet these specifications, the technique of MOS CurrentMode Logic (MCML) can be used. MCML has emerged as a logic style that canachieve the much needed high speeds while consuming less power than conventionalCMOS circuits at these high frequencies. MCML circuits are characterized by their lowsupply noise generation and high noise immunity, thus enabling the integration ofanalog and digital blocks on the same chip.Based on SMIC0.18um1P6M standard CMOS process and MOS Current ModeLogic, a16bit,1GSPS current-steering D/A converter is designed. The segmentedstructure is6-5-5, use MCML to implement the thermometer decoder andbinary-weighted decoder. A current source layout strategy is proposed, which caneffectively reduce the systematic and graded errors. To increase the dynamicperformance, a low swing and low cross current switch drive schematic is designed.Provide metal fuse calibration schematic makes sure the current unit matching.Analog supply is3.3V and digital supply is1.8V. The chip has a full-scale outputcurrent10mA, upper bound of INL4LSB and DNL3LSB before calibration. At1GHzsample rate, SFDR of104.4dB, ENOB of13.31bit, setup time is2.82ns and powerdissipation of245.36mW. The area of the chip is2mm×1.3mm.