Characteristic Analysis Of Several Nano-scale MOS Current Mode Logic

High-speed low-power VLSI technology has become a trend now. Because of constant static power consumption, MCML (MOS Current Mode logic) has attracted attention. However, the characteristics of MCML circuits were affected by multiple parameters which have coupling between each other to a large extent, thus result in its high degree of design complexity and limit its wide application. Small-signal circuit analysis and simulation methods were used in this paper to make a deeply insight into the impact of the four important factors on MCML performance. By analyzing causation, extent and adjustment methods of these four factors impacting on MCML performance as well as by putting the primary and secondary relationships between them in order, the design methods of the MCML circuit were generalized in this paper, and an effective design procedure was found out. Based on BPTM (Berkeley Predictive Technology Model) of CMOS process in nano-scale and the Hspice circuit simulation software, the technology scale shrinking and power supply voltage drop effects on FO4 (fan-out four) MCML and standards CMOS inverter were compared in this paper. Simulation results showed that the performance improvement of nano-scale MCML circuit was faster than that of the standard CMOS circuits as the technology scale shrink and the power supply voltage drop down.