Analysis of Effects of Power Supply Noise on Propagation Delay

Today's very deep sub-micron technologies enable highly complex chip designs that operate at very high frequencies. Transistor dimensions have shrunk to a few tens of nanometers. Therefore, to ensure reliable chip operation and to reduce both dynamic and static power consumption the chip's supply voltage must be scaled down. This scaling of the maximum supply voltage reduces noise margins and makes designs susecptible to power supply noise. Power supply noise is the variation in the chip power supply i.e. IR and Ldi/dt drops due to the power grid and package parasitics. As the supply voltage drops it causes an increase in the propogation delay. Transistion-fault testing is a widely used test technique in the industry that can detect delay defects. In order to minimize the testing overhead, ATPG tools generate vectors that target multiple faults at the same time. However, these vectors cause excessive switching in the circuit and therefore increase power supply noise. As the propogation delay increases with power supply noise this can lead to a significant overkill when using transistion test patterns. In order to accurately measure this noise one would need to run dynamic circuit simulations, which is infeasible even for a small portion of the chip. Previous work has demontrated a convolution-based technique that can be used to compute transient current and voltage at the power pads and at different locations on the power grid. In this work, we use this computation technique to analyze the effect of power supply noise on path propogation delay. We also compare the delays computed using the convolution based technique to full-chip transient simulations.