On-die Power-supply Noise Measurement Techniques

With the rapid development of very large scle integrated circuits(VLSI)technol-ogy,the scale of the system on chip(So C)has become larger and the integration level has become higher,resulting in the need for more complicated on-chip power delivery networks(PDN).At the same time,the noise between the power domains will produce crosstalk problems,which will not only affect the performance of the system,but even cause the system’s functional errors in the case of severe noise.In order to solve the sys-tem noise problem better during the design iteration of the chip,it is necessary to measure and analyze the on-die noise.However,the on-die noise power spectrum bandwidth can be extended from DC to one hundred GHz.Due to the presence of parasitic resistance,capacitance and inductance of the on-chip wiring and packaging,it is difficult to mea-sure the true value of the on-die noise off-chip.Therefore,in the scene that requires a more accurate understanding of on-die noise characteristics,especially in scenarios where high-frequency noise characteristics are more concerned,the technology to complete noise measurement on-chip is very necessary and worthy of further study.Firstly,this dissertation introduces and analyzes the basic principles and methods of on-chip noise measurement technology.It mainly includes sorting and classifying the cir-cuit structure corresponding to different measurement methods and different noise char-acteristics,and analyzing in detail and systematically summarizing the advantages and disadvantages of early on-chip noise measurement research works.Then this dissertation proposes a voltage-controlled oscillator(VCO)-based on-chip noise measurement system design scheme that combines compressed sensing(CS)technology to reduce measurement time and improve measurement accuracy.The main innovations in the designs include:1)Through theoretical research,it is proved that the autocovariance function can obtain a lower noise floor in the noise measurement system than the autocorrelation func-tion,and can eliminate the noise introduced by the measurement system itself,and the correctness of the theoretical analysis is verified by the chip test results.2)A VCO-based phase quantizer without additional clean power and reference voltage is designed to achieve six levels of quantization of the output signal of a high-gain VCO,which effectively improves the measurement accuracy of the on-chip noise measure-ment system.3)In order to further improve the accuracy of the measurement system,using VCO phase noise as a natural dither,a multi-slice quantization structure is proposed.4)Since the noise with periodic stationary characteristics in the on-chip power domain is sparse in the frequency domain,compressed sensing technology can be used to fur-ther reduce the measurement time.In the autocorrelation sampling clock generator,a nonuniform sampling clock mode is proposed to achieve compressive measurement.5)Design a calibration-free autocorrelation sampling clock generator,the limitation on the clock sampling rate in the conventional autocorrelation sampling clock generator is discovered and removed,and the sampling rate of the measurement system is effec-tively increased to reduce the measurement time.The above design have been fabricated and tested in a 40 nm CMOS process to ver-ify the innovative idea of on-chip noise measurement.The 20 GHz on-die PSN analyzer achieves 0.23 m V2/√(MHz)noise floor and 2MHz spectral resolution within 21-second measurement time with compression ratio of 8.Compared with other prior works,the performance presented in this thesis has reached a higher level in the field of power sup-ply noise measurement.