Power supply noise reduction techniques for mixed signal SoCs

Systems-on-Chip (SoCs) consist predominantly of CMOS digital logic circuits. CMOS gates have attractive features of low power consumption, high packing density, ease of design, etc. Most of the power consumed by digital CMOS gates is due to displacement currents, drawn during output state transitions, charging and discharging wires and device capacitances. These increase linearly with operating frequency and flow through the power supply and ground lines. The displacement currents flow through parasitic inductances and the on-chip capacitances of the power supply and ground (PG) network causing ringing (di/dt ) and IR drop. This unwanted variation in the PG network is found to be the most dominant source of the substrate noise currents injected into the substrate. The noise currents thus injected flow through the substrate and are picked up by the sensitive analog circuits, causing degradation in performance of voltage-controlled oscillators (VCOs) (jitter), Analog-to-Digital Converters (dynamic range) etc.;Existing techniques that minimize switching-noise generated, such as current steering logic (CSL), current balanced logic (CBL) etc. require considerably more power than traditional CMOS implementations. We present a logic family called current steering CMOS (CS-CMOS), which not only reduces the switching noise (10X) but also delivers 5X higher performance compared to existing families without an increase in power consumption. Experimental results comparing 15 stage ring oscillators for CSL and CS-CMOS in 0.18 microm GSMC process are presented. The CSL inverter exhibits an energy-delay-product of 6.5 fJ*ns as compared to CS-CMOS of 1.52 fJ*nS. A cell library of CS-CMOS gates is created, synthesized and proven to have the similar 5X improvement over CSL on existing benchmarks, decimation filters and frequency dividers.;Another technique is investigated in which the noise generated due to digital CMOS gates is de-coupled from the rest of the blocks. A noise localization technique using on-chip active inductors is proposed. This would make the noise generated by the digital gates to remain in the region of the digital gates. This active inductor is designed to have minimum overhead in terms of voltage headroom and area. Simulations of benchmark digital gates, frequency dividers and buffers demonstrate about 30 dB reduction of noise with this technique. Measured results from a test-chip carrying this design further demonstrate the functionality of this inductor.