Analysis About The Influence Of Power Supply Noise And Signaling Encoding On High-speed Full Link Performance

With the digital signal rate faster and faster,serial bus begins to occupy the mainstream market,however,there are still some parallel buses playing an important role,such as DDR4,which is the fourth generation product of double data rate synchronous dynamic random access memory.When the bus bit width increases,power supply noise of high-speed parallel bus DDR4 will also increase.The low supply voltage and the low noise tolerance of DDR4 result in a worse signal quality under the influence of power supply noise.In order to fully evaluate the performance of DDR4,the signal integrity issues of the passive link and the power integrity issues of the power distribution network need to be analyzed collaboratively.Signal integrity engineers mainly focus on the performance of high-speed systems,and generally use eye diagrams to measure system performance.The method that using SPICE simulation of a large number of pseudo random bit sequence to obtain traditional eye diagram takes a lot of time,and may also be unable to get the worst-case of the eye,which leads to the traditional eye can't meet the requirements of designers to measure system performance.Therefore,the signal integrity engineers urgently need an algorithm to obtain the worst-case eye and bit error rate eye under the influence of power supply noise and passive link noise.In this paper,some quick and efficient methods to solve the worst-case eye and bit error rate eye are proposed,we take the high-speed parallel link DDR4 as an example to introduce the methods,and then analyze the effects of power supply noise and coding on its performance.In order to evaluate the design of PDN,this paper proposes an algorithm which can quickly and accurately predict the worst power supply noise of high-speed systems and the input data pattern that can excite worst power noise.To obtain the power supply noise,the algorithm uses the convolution of the time-domain impedance of PDN and the modeled switch current,and the focus of the algorithm is to model the switch current quickly and accurately.In this paper,the DER(Double Edge Responses)algorithm,a fast time-domain algorithm,is used to obtain the worst-case and worst data pattern of the passive link.The worst-case of the passive link and the impact of worst power supply noise on the channel are superimposed to obtain the worst-case eye diagrams of high-speed parallel links DDR4,and then the input pattern that can excite worst-case of full links is analyzed.Combining the DER method and the statistical domain idea,the probability distribution of the noise of the DDR4 passive link and the probability distribution of the noise which is power supply noise coupled to the channel are achieved,and naturally the bit error rate is obtained according to the probability distribution.Finally,this paper analyzes the effect of DBI(Data Bus Inversion)coding on the eye diagram of high-speed parallel link DDR4.In this paper,the simulation software PDN_BER_Tools based on Matlab-GUI(Matlab Graphical User Interface)is developed,and the results of the worst eye and the bit error rate eye are analyzed according to the DDR4 simulation platform,which verify the validity of the algorithm.