Integrated CMP metrology and modeling with respect to circuit performance

As the semiconductor industry keeps its scaling efforts down to the sub-90nm technology node on the roadmap, the process and materials in the integration are being pushed to the limits. Integrated Circuits (IC) designers nowadays require more than 30% performance improvement from interconnects each technology generation. The introduction of copper and low-k materials in the last few years has been the key move toward that objective. Particularly Chemical-Mechanical Polishing (CMP) has been the enabling technique to planarize the metal surface and define metal layer thickness in contemporary copper Back-End-of-Line (BEOL) technology. However, CMP also introduces undesirable side-effects, including dielectric erosion and metal dishing, which degrade the process quality, cause significant yield losses in BEOL, and negatively affect interconnect performance.; The central theme of this thesis is the integrated metrology and modeling analysis in copper Chemical Mechanical Polishing (CMP) process towards optimizing interconnect and circuit performance. This work pursues special testing mask design and data analyzing techniques that are used to identify and model the sources of yield limiting factors in copper CMP---namely oxide erosion and copper dishing. The main contributions of the thesis are the following: by applying special test structures design and data analysis, we developed and validated a model for copper dishing, and use that as the basis for process optimization and interconnect performance estimation. As the prerequisite and benefit of our effort, we applied the library-based scatterometry to monitor oxide CMP profile evolution; realized the model-based profile extraction using the e-test data in copper CMP. We set up the process optimization framework based on the contemporary models. Finally, we linked these CMP technology issues to circuit and interconnect design considerations through simulation work.; The validated dishing model integrated with other models and optimization frameworks serve the goal of design for manufacturability in the Back-End-of-the-Line Process. The process models and optimization framework developed in this thesis provide insight into the observables in the state-of-the-art CMP process. By transferring theses principles into the realm of production, these building blocks can provide the opportunity for the process and integrated circuit designers to integrate and fuse information from both perspectives, thus improve the fabrication yield and circuit efficiency in the long term.