Low Dielectric Constant Process Integrated Circuit Packaging Technology

As integrate circuit(IC) is developing to multi function and mini size, characteristic dimension will change to small,more and more low-k material will be applied in semiconducer industry.But the current low-k material is not perfect selection,much quality issue were happened.As the brittleness of low-k material,the traditional wire bonding parameter often lead to die pad crack or Au-AL matter bad;after used low-k material,die size,die pad opening and die pad pitch change to more little,wire change to lengther and density change to more higher,it' s new challenge for molding and wire bonding;at the same time, low-k material also require to control the thermal stress in package.To get solution,the thesis will focus on wire bonding and molding to study.For wire bonding,we got methods to avoid low-k material layer crack and IMC crack by gold wire selection,capillary design optimization,and wire bonding process window study;Wire sweep issue was declined,after use reverse wire bonding technology to get low wire loop,define high wire loop and low wire loop between neighbour wires to reduce wire cross and split transfer course into several segments by different transfer speed to control mold flow;For molding and to different packages,as a physical method,add suitable presser during different cure process,it can reduce warpage value;As chemical methods,optimized component of molding compound or added flexiblier,it can decline thermal stress and warpage.Through new material evaluation procedure and mass production experience,validated above methods are feasible and available.