Research On High Performance Motion Estimation Circuit Design Technology For UHDTV

Compared with the previous H.264 / AVC digital video coding standard,the high efficiency video coding(H.265 / HEVC)has superior video compression rate.At the same time,ultra-high definition(UHD)video applications because of the development of display technology is being applied to various products.UHD video with coding characteristic of the large search range proposed a huge challenge on the design and implementation of the HEVC's most complex part,motion estimation.In this paper,a hardware-friendly two-layer HEVC motion estimation algorithm for UHD is proposed,and a hybrid search algorithm combining full search,downsampling and hexagon fast search is designed.The proposed algorithm is integrated into the HEVC software model(HM),and the UHD video sequences are used to carry out the simulation test.The results show that the proposed algorithm can reduce the computational complexity by 96% compared to the full search algorithm,and only 0.61% RD-rate loss.Compared with the previous algorithms,the percentage reduction in computation is increased by 6%,and the image quality loss is reduced by 1.5%.Based on the previously proposed algorithm,this paper completes the high-performance motion estimation circuit architecture design and VLSI implementation.According to the characteristics of the hybrid search strategy,by dividing the search sub-interval,the circuit architecture to achieve reuse of pixel data,improve the circuit utilization.VLSI of SMIC 65 nm process shows that when the operating frequency of the circuit is 320 MHz,the real time coding of the UHD @ 60 fps video sequence can be completed.The circuit logic consumption is 1083 K,and the calculation logic utilization is 0.86,so the circuit's processing ability is increased compared with the previous circuits.Finally,utilizing the complexity of the circuit interconnection for the motion estimation circuit,the implementation of the two-layer 3D VLSI is completed.The results show that the implementation of the two-layer 3D circuit can reduce the average interconnect length by 12% and 47% area.