Modeling and technology CAD for scaled BiCMOS integrated circuits

This dissertation describes development and assessment of bipolar junction transistor (BJT) models and simulation tools for technology computer-aided design (CAD) of scaled BiCMOS integrated circuits (ICs). Optimization of the conventional BiCMOS design for supply voltage scaling is analyzed using MMSPICE, a semi-numerical mixed-mode device/circuit simulator. Device/circuit simulations give physical insights concerning design optimization, and suggest optimal design involving variations in gate layout and polysilicon emitter process. The optimal design is shown by simulations to be superior to the counterpart CMOS gate at low supply voltage (3.3 V) in regard to propagation delay. A simple yet accurate model for the parasitic substrate pnp BJT, which can be activated by (quasi-) saturation of the npn transistor and hence can be problematic for reliable BiCMOS gate operation, is developed. The semi-empirical model is defined based on insights gained by purely numerical device simulations (with PISCES) and is verified by measurements. The physical MMSPICE BJT model is benchmarked by demonstrating important advantages of it, which include model scalability and ease of parameter tuning, and by qualifying its disadvantages, which include inaccuracy in hard saturation and increases in run-time. It seems that the advantages of the MMSPICE BJT model outweigh the disadvantages and hence it is possibly a viable alternative to the ubiquitous SPICE Gummel-Poon model. A methodology for statistical (Monte Carlo) simulation and sensitivity analysis is developed by exploiting unique advantages of MMSPICE and SUMM, its model parameter evaluator, applied to IC TCAD. The novel methodology reliably and efficiently relates device/circuit performance directly to measurable process parameters since MMSPICE/SUMM implicitly accounts for physical correlations among device model parameters. The computational efficiency permits use of a simple Monte Carlo technique involving random generation of process parameters for the statistical simulation. The utility of the TCAD methodology is demonstrated by predicting IC parametric yields and sensitivities of device/circuit performance to process parameters in an actual technology.