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High-speed analog RF front-end circuit design

Posted on:2006-10-27Degree:Ph.DType:Thesis
University:University of MinnesotaCandidate:Jung, ByunghooFull Text:PDF
GTID:2458390008975164Subject:Engineering
Abstract/Summary:
Most recent data processing and communication systems handle data in the digital domain. But in all cases, the signals at the interfaces are in analog format. Ironically, the main driving force behind the development of analog high frequency circuits is the increasing demand for high-speed digital communication. In digital wireless communication, the available frequency bands are crowded and the demand for higher data rates is ever increasing. New systems are seeking to occupy higher carrier frequencies and use more data bandwidth. These high frequency wide-band wireless communication systems pose interesting challenges to analog RF circuit and system designers. Many digital serial link systems are now focused on attaining several tens of Gbps data rates. And all high-speed digital links require high performance high-speed analog circuits. As the analog/RF portion has to handle the highest frequency signal in the system and satisfy stringent specifications, it consumes a large fraction of total power. Over the recent years, there has been significant improvement in the research of high-speed analog circuit designs. However, as communication systems and digital serial links become faster and more sophisticated, development of new high-speed circuits and system designs become more of a necessity.; This thesis focuses on three separate topics that are important to both wireless and wireline communication systems. Chapter 2 presents two new topologies for LNA design. The first topology, based on an inductive source degeneration technique, proves that a gm boosting technique using increased input impedance improves the NF. The second topology, a complementary cross-coupled topology, provides easy impedance matching, high linearity and good NF. The detailed theoretical analysis of NF, gain, linearity and power efficiency is discussed. In Chapter 3, we describe the design of an integrated VCO using capacitive degeneration. Theoretical analysis and simulation results show that the oscillators using capacitive degeneration technique can out-perform traditional oscillators using cross-coupled gm cell at frequencies close to fT. In Chapter 4, we discuss the design issues in high-speed CDR. The various design techniques to achieve wide bandwidth and small interference are discussed. The first 20Gbps CDR in a 47 GHz fT technology is also presented.
Keywords/Search Tags:High-speed, Communication systems, Digital, Data, Circuit
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