Board Level HALT Fixture Design Based On High Speed Digital Circuit Technology

Enterprise network exchanger is quite complicated in the system. During the R&D process of the enterprise network exchanger, HALT (Highly accelerated life test) is usually conducted with the veneer as the target to find out the flaws, and improving the reliability of products. In this project, it is mainly conducted by HUAWEI TECHNOLOGIES CO., LTD. for enhancing the reliability of veneer, so as to improve the reliability of its enterprise network exchanger and save the test cost.In this paper, the board-level HALT is proposed, namely the way of using the entire exchanger for HALT is changed in the test. Instead, HALT is conducted with the veneer as the target. HALT fixture circuit is designed for realizing the transformation of related high-speed signals, so as to meet the demands of board-level HALT.At first, related knowledge about HALT is introduced, and disadvantages of HALT in stress transfer are discussed on this basis. The board-level HALT is proposed, Related knowledge about the signal integrity and power integrity that are closely related to the high-speed digital circuit is discussed and analyzed according to the demands of the design for board-level HALT fixture high-speed circuit. On this basis, overall plans of board-level HALT fixture is proposed, and detailed hardware design of system is offered, including the design and optimization of business management channel, monitoring channel,25gbps business loop, power design; The PCB is drawed and the simulation of power was carried out. The transferring effect of the board-level HALT stress is analyzed, the fixture circuit is tested and debugged, and the parameter of business channels is modified. Finally, the entire HALT fixture is verified with HALT test.According to the test results, the board-level halt fixture meets the demands on the HALT test of enterprise network exchange in expected effect.