Research On Key Techniques Of High Speed And High Performance Direct Digital Frequency Synthesizer (DDS)

High speed high performance Direct Digital Frequency Synthesizer(DDS)is a key circuit for modern communication and radar systems.With the continuously developing of digitization and informatization,the needs for higher frequency and higher performance DDS will become more intense.To implement a high speed high performance DDS(which embedded with a high speed DAC)needs many kinds of key techniques,such as system level design,arithmetic design and circuit level implementation,high speed analog circuit design,layout and mixed signal IC simulation,etc.This work takes all these techniques as the research contents,and focuses on system structure design and digital pre-distortion function implementation,high efficient phase to amplitude Coordinated Rotation Digital Computer(CORDIC)arithmetic design,low power circuit level implementation,and high speed current-steering D/A converter design,etc.A 2.5GHz DDS has been designed and implemented in 0.18?m CMOS.The measured result verifies all the researched techniques are efficient and utilizable.The contents are shown as follows.1.Based on a 0.18?m CMOS technology,the system level structure and function block implementation scheme of a 2.5GHz DDS have been designed.In order to reduce clock-induced-spurs in DDS`s output spectrum,a digital pre-distortion cancellation technique which is used to cancel spurs has been utilized.The quantization error of the digital pre-distortion signal has been analyzed theoretically.Then the mathematical expression,MATLAB simulation results,and the circuit level implementation scheme have been obtained.A pre-distortion operation flow has been summarized,and the measured results show that the digital spur cancellation method improves more than 20 dB for SFDR performance compared to its intrinsic performance.2.An optimized CORDIC arithmetic has been designed and then applied to the 2.5GHz DDS.The optimized CORDIC arithmetic refers to the excess-four arithmetic(which was first presented at ISSCC2011),and two optimizations have been implemented to save the arithmetic's hardware consumption.The first one showes that some middle values are obtained from multiplication operation instead of the ROM lookup table,and the second one showes that the structure of excess-four cell is optimized.Simulation results and measured results all show that the optimized CORDIC arithmetic has a smaller chip area and lower power consumption compared to the reference CORDIC arithmetic.The power merit factor is as low as 0.0432mW/MHz which is the lowest one among all the present published literatures.A time interleaved architecture(with an interleave factor of 8)has been utilized to achieve high speed as 2.5GHz,and the architecture has low power consumption by letting most of the channel execute interpolitation instead of multiplication.3.A 2.5GHz 14-bit current-steering architecture D/A converter(DAC)with 8 to 1 MUX has been designed.A bias circuit which ensures the PMOS current source to obtain a larger output impedance under every PVT(process,source voltage and temperature)corner has also been designed.Larger output impedance means better SFDR performance.A proper timing sequence is designed to ensure reliable data synthesis.The DAC is embedded in the 2.5GHz DDS,and measured performance is SFDR > 40dB(with and without DEM)for output signal frequencies up to 1GHz.Comparing with other present published DACs with non-analog-resample structure(means return-to-zero or quad-switch structure is unutilized),this paper DAC's clock frequency(2.5GHz)and higher output frequency SFDR(>40dB,up to 1GHz)have more competitive power.This paper DAC is one of the fastest DAC among all the published DACs based on 0.18?m CMOS.4.A multi-chip synchronization circuit based on diversity technique has been designed.Like diversity technique in communication,at the master IC chip's transmitter,two periodic synchronization signals(with a set delay time between them)have been sent as the synchronization reference signal.At every IC chips' receiver end,a searching method(by internal state machine)is used to obtain the suitable receiving clock for the two synchronization signals' reliable receiving,and the two received external synchronization signals and an internal generated synchronization signal will be time aligned.Only one of them is selected to reset the internal frequency divider periodically.The two received synchronization signals are monitored,if any receiving error occurs,it will be switched to use the other one,if two external synchronization signals have both got receiving errors,the internal synchronization signal will be switched and an indication signal will be sent to let the user known.This multi-chip synchronization system can achieve a reliable performance.The periodic and occasional receiving error or long time receiving error(wire disconnection)will not interrupt the synchronization state.