| Precise time interval measurement is very important in many experimental and applied systems. Time-to-digital converters (TDC) are one type of such measurement systems, which convert the arrival time difference between two input pulses into digital codes. TDCs find various applications in high energy particle detectors, laser range finders, digital storage oscilloscopes, also in all-digital phase lock loops. Since the performance of a TDC greatly affects the performance of the overall system, it attracts a great deal of research efforts.;TDCs based on delay elements are currently dominant compared to other analog-circuit-intensive implementations, because of their design simplicity and that their resolution is inherently enhanced by technology advancement. However, there are challenges on designing high-resolution delay-line-based TDCs. First, when the full scale of the TDC is increased, the number of delay cells (basic time measurement units) have to be increased exponentially, which greatly increases the power consumption. Even worse, when the number of delay cells increases, circuit noises and mismatch-induced nonlinearity from each cell accumulate along the chain and worsen the resolution and linearity of the TDC. Besides, the achievable finest resolution (i.e., the least significant bit, LSB) of the delay-line-based TDCs is limited by the minimum delay of the delay cells, which is process-dependent. Although a number of methods are proposed previously to improve the time resolution beyond the process restriction, there are shortcomings on those architectures, for example, the increase of delay elements needed for generating refined time reference.;In this thesis, we focus on the design of high resolution TDCs. First, to decrease the number of delay elements in the TDC, a two-stage Vernier Parallel Delay Line (VPDL) based TDC is proposed. By cascading two sets of parallel delay lines with slightly difference in resolution, the overall resolution of the TDC is much finer than that of the two sets. By using the first stage delay line as the time reference of the coarse TDC, the number of delay elements is greatly reduced when compared to single stage ones. Besides that, the VPDL makes the delay step sizes similar between stages utilizing Vernier principle, which relaxes the step size requirement of the delay elements, also facilitating design re-use of delay cells among two stages.;Second, to improve the linearity and offset problems in the proposed TDC architecture, a foreground calibration scheme is proposed. By making the delay cells discretely-tunable with equal step, a digital feedback loop can be formed to tune the delay/ measure the step size of each step, then tune the delay of each cell according to the information. The proposed scheme uses the discretely-tunable delay steps to tune the delay, also as the reference of calibration, so no accurate timing signal is needed from internal/external of the TDC. This simplifies the calibration process.;Third, a behavioral modeling approach is proposed to provide a quick way for system design and functional verification. The proposed modeling approach transforms the input time difference at each clock cycle into amplitude, so that the tradeoff between accuracy and simulation step size, problems on modeling and transient simulation of calibration logic that exist in direct modeling approach are alleviated.;To prove the proposed techniques, a 6-bit prototype TDC is fabricated in a 0.13mum CMOS technology, achieving a LSB of 5ps, DNL of 0.6LSB and single-shot precision of 0.4LSB in measurement. |
