Research On High-resolution Time Interval Measurement Technology

Time interval measurement,also called time-to-digital conversion,is usually used to convert the time interval between physical events into digital values.Time interval measurement is widely used in the area of astronomical experiment,nuclear physics experiment,nuclear medicine imaging,weapon strike and integrated circuit test,and the performance of the applications is directly influenced by the resolution of time interval measurement.Researches of high-resolution time interval measurement at home and abroad are focused on employing ASIC technique to customize special chips.However,special chip customized by ASIC technique is high in development cost and long in time to market,which limits the development of time interval measurement.In recent years,with the continuous development of commercial CMOS technology,employing FPGA chip to realize time interval measurement system has gradually become popular.However,most of the researches implemented on FPGA chip are realized by using special delay elements.Influenced by the time delay and the delay linearity of the delay elements,it is a difficult problem for time interval measurement method implemented on FPGA chip to obtain a resolution better than 10 ps.What is more,the time delay of the delay elements are sencitive to varitions of temperature and voltage,which increases the measurement error.In views of the problems above,this paper conducts researches on time interval measurement methods based on FPGA chip.First,routing resources of the FPGA chip is studied,and methods of employing routing resources to realize time interval measurement is discussed.Then,research of the internal structure of the FPGA chip is carried,and novel time interval measurement method is explored taking advantage of the structural feature of the FPGA chips.For system evaluation,high-precision time interval generating method is also studied,and a testing bench is built to evaluate the performance of the time interval measurement method.Finally,this paper analyzes the influence of manufacturing process to the performance of time interval measurement method.The main work and innovations of the paper are described in the following.1.This paper proposes a method that using routing resources in the FPGA chip to build delay line,and a time interval measurement system(FIRRT)is realized based on the method.To improve the delay linearity of the routing paths,this paper modifies the structure of the famous vernier delay line,which adds bridge units into the delay lines to adjust the routing strategy of the router.The bridge units are realized by the programmable input output delay elements inside the FPGA chip.What's more,manual placement and manual routing are performed to further improve the delay linearity.2.The large scale multi-phase parallel measurement(LSPM)method is presented,and the implementation method of the LSPM principle is also studied.This paper describes the generating method of large scale multi-phase signal,the design of large scale parallel counters and design of the measurement structure.The influence of different measurement structure and inputting locations of the time interval signal to the theoretical resolution is also analyzed.What is more,several clock generating methods are also compared.A time interval measureemnt system is realized based on the LSPM principle.The system uses the routing paths between the time interval signal and the counters to construct independent delay elements,and it also acquires both large measurement range and high resolution in a single measurement.3.This paper also conducts researches on time interval generating method.The vernier delay line is used to generate time intervals,and the principle of Quantified Phase Shift Resolution(QPSR)is also presented.Time interval generating system based on the two methods are realized,and the time resolution of the two systems are 1.02 ps.and 3.93 ps,respectively.4.Based on the time interval generating method,this paper builds testing bench to evaluate the performance of the FIRRT and LSPM-TDC.Measurement results indicate that FIRRT provides a resolution of 9 ps,and the DNL and INL are 0.11 LSB and 0.66 LSB,respectively.LSPM offers a resolution of 7.4 ps,the DNL is-0.74 ~ +0.74 LSB,and the INL is-1.52~+1.57 LSB.Compared with other FPFA-TDC systems,the proposed LSPM-TDC and FIRRT have better temperature and voltage stability.What's more,FIRRT has better stability than LSPM-TDC.5.To analyze the influence of manufacturing process to the FIRRT and LSPM-TDC,this paper also implements the FIRRT and LSPM-TDC on FPGA chips with different manufacturing processes,including 40 nm,28 nm and 20 nm.Experiment results show that the performance of FIRRT is not evidently influenced by process.However,the resolution of the LSPM-TDC improves with the improvement of manufacturing process in most conditions.The LSPM-TDC implemented on the 28 nm Kintex-7 FPGA chip obtains a high resolution of 1.29 ps.In summary,this paper not only presented a new realization method of vernier delay line based on routing resources,but also proposed the LSPM principle.Moreover,the TDC with 1.29 ps resolution is realized on the FPGA chip.Experiment results verified the performance of both the proposed time interval measurement method and the realized TDCs.