Design and implementation of a high resolution, multi-hit time-to-digital converter (TDC) on FPGA

The notion of timing and time measurement has its significance in many areas of science and engineering. A time interval is defined as the time elapsed between occurrences of two physical events, be it the propagation delay of a logic block in digital electronic circuits from an input to the output, the jitter in a periodic signal such as the system clock, or the distance in time between two or more adjacent particles liberated from the collision point in Time-Of-Flight experiments. A Time-to-Digital Converter (TDC), also referred as Time Interval Meter (TIM), is the electronic circuit designed to measure the time elapsed between two tinning events/pulses. A TDC circuit usually consists of two time interpolating modules namely the fine time interpolator module used to slice the period of the reference clock into smaller time steps, and the coarse interpolator (binary counter) used to achieve coarse measurement of time with a resolution equal to the reference clock period. The various characteristic parameters of a TDC circuit include the resolution of the measurement, the precision/accuracy of the measurements, the maximum measurable interval (dynamic range), non-linearity of the conversion process, and the dead time. For multi-hit TDC circuits capable of measuring more than one time interval sequentially, pulse pair resolution is another parameter of importance.; Over the years, a lot of research efforts have been devoted to come up with new or more improved TDC structures. The many TDC solutions proposed by researchers involve design methods that vary from the early analog-based solutions to the recent partial or fully digital ones. The time-to-amplitude conversion and the time interval stretching are the famous analog-based time interpolation methods used in many TDC circuits. On the digital side, the interpolation solutions are mainly achieved by means of delay lines with resolutions proportional to single gate delay or the variants of delay lines such as the Vernier principle with sub-gate delay resolutions. Other complex structures with improved characteristics have also been proposed.; The proposed TDC circuit in this research work is based on a new time interpolator utilizing the Vernier principle in order to achieve the high measurement resolution. The time interpolator is an array of Vernier delay lines (VDL), also seen as matrix of Vernier delay cells, with the interconnection between successive rows achieved through the first delay cells of each line with a common reference clock line shared among all. The delay matrix measures the distance in time between the rising edges of the data and the subsequent clock signals applied at the respective data and clock inputs of the matrix. The matrix structure breaks this interval into two-level time bins of tau Y = tL and tauX = tL - tB with tB and tL as the propagation delays of the buffer and latch elements of the matrix delay cells. The vertical interconnection provides a propagation path with larger time bin tauY whereas the single-shot measurement resolution tauX is achieved by horizontal propagation throughout the Vernier delay lines. The TDC circuit measures an interval of time between two incoming pulses by taking the difference in corresponding arrival times with respect to some reference point.; The TDC circuit is implemented on a low-cost SPARTAN-3 FPGA from the SPARTAN(TM) family by XILINX in an attempt to exploit the recent advances in programmable logic devices. The measurement resolution attained is tau X = 113ps in simulation, whereas the experimental results give tau X ∼ 75ps. The TDC circuit is capable of measuring multiple sequential intervals with a PPR ∼ 7.5 ns. The average deviation of a measured time interval T from its ideal value is ∼1.5% for intervals larger than 12.0 ns and 3.5% for intervals with ideal lengths less than 12.Ons. The main sources of measurement error are attributed to existence of clock skew on clock lines in the delay m...