Research On Key Technique Of Testing For The Three Dimensional Integrated Circuits

Three dimensional integrated circuits greatly enhance the number of transistor design through vertical integration, which is considered to be one important technology that extends the Moore’s Law. Compared with two-dimensional integrated circuits, three-dimensional integrated circuit (3D IC) has the advantages of reducing wire length and delay, decreasing power consumption budget, increasing communication bandwidth and allowing heterogeneous integration that incompatible manufacturing can be combined in a single 3D-IC etc. It has been estimated that the switch to vertical interconnects may reduce power consumption in half, increase bandwidth by a factor of eight, and shrink memory stacks by some 35 percent. However, on one hand,3D IC binds multiple dies vertically and the integration is far higher than 2D IC, on the other hand, the test pins can only be placed around the dies, thus test resources assigned to each module are relatively less and the test controllability, observability are degraded. The traditional 2D IC design for testability can not fully deal with the fault in 3D IC. Further more, the mid-bond test is the special test insertion beyond the traditional 2D test flows and the mid-bond test is much more complicated. Through silicon via is susceptible to defects for immature manufacturing process. With the number of dies stacked increasing, the yield loss caused by TSV failure exponentially rises.To solve the problem above, in this dissertation, considering the probability and cost of failed bonding in mid-bond process, an optimized stacking order is proposed to improve the yield of 3D IC. Integer Linear Programming is proposed to optimize the test architecture and test schedule during the mid-bond process of 3D IC. One non-invasive test method for through silicon via is also researched and a pulse shrinkage based pre-bond TSV test scheme is proposed to deal with the resistive open fault and leakage fault. The main contribution in the dissertation is as follows:(1) Optimized Stacking Order for 3D ICs Considering the Probability and Cost of Failed Bonding. Aiming at the low yield in 3D IC, this paper proposed a novel rearranged stacking scheme which estimated the probability and cost of failed bonding in each stacking step and optimize the mid-bond order to screen out the failed component as early as possible. The notable difference between 3D testing flow and 2D testing flow mainly lies in the mid-bond test, in which the stacking yield can be further enhanced through optimized bonding arrangement. The effect of the rearranged stacking has been extensively analyzed using the yield model and cost model of 3D IC considering different process parameters such as die yield, stacking size, failure rate and redundancy degree of TSVs. In contrast to the existing sequential stacking, experimental results demonstrated that the proposed rearranged stacking method is only half that of the sequential stacking in terms of failed area ratio (FAR).(2) A scheme of 3D integrated circuits testing application time optimization for mid-bond test. Aiming at the long test application time, an optimization scheme for mid-bond test time in 3D IC was proposed. Mid-bond test is able to detect the defect introduced by wafer thinning, TSV alignment and bonding process earlier. However, test application time and test power consumption will also increase significantly. With the consideration of the test TSVs, test pins and power consumption constraints, Integer Linear Programming is used to optimize the testing time and stack architecture. Unlike the existing post-bond test only, with considering mid-bond test, experimental results show that the test application time of the diamond structure and the inverted Pyramid structure is 4.39% and 40.72% less than the average test application time of the Pyramid structure. Considering the test power consumption constraint, the test application time of the Pyramid structure increases by 10.07%, however, the test application time of the diamond structure and the inverted Pyramid structure increases by 4.34% and 2.65% respectively. Compared with the Pyramid structure, the number of test TSV increases by 11.84% and 52.24% in diamond structure and the inverted Pyramid structure, and the number of test pin reduces by 10.87% and 7.25% respectively.(3) Pulse shrinkage based pre-bond through silicon vias test in 3D IC. Aiming at the low yield and difficulty in test access of TSV, a pulse shrinkage based pre-bond through silicon via test scheme was proposed. A non-invasive approach for pre-bond TSV test based on pulse shrinkage is proposed to detect resistive open and leakage fault. Defects in TSV not only lead to variation in the propagation delay but also in the transition delay of the net connected to the TSV. TSVs are used as capacitive loads of their driving gates, then the pulse visiting the cyclic shrinkage cells will be shrunk until it vanishes completely. The shrinkage amount is digitized into a digital code to compare with an expected value of fault free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the high resolution, wide detection range, high flexibility and the effectiveness in the detection of resistive open defects 0.2kΩ above and equivalent leakage resistance less than 40MΩ. The estimated design for testability area cost of our method is negligible for realistic dies.