On-Chip Circuits for Jitter Measurement and Signal Capture with Sub-Picosecond Resolution

This thesis focuses on the design of on-chip timing measurement circuits with sub- picosecond resolution. First, a review of the most common techniques in the literature has been presented. Then, an on-chip oscilloscope circuit is proposed to capture the eye diagram of differential signals. Experimental results in a 65-nm CMOS technology reveal that the 0:0024-mm2 circuit can measure the eye diagram of a 12:5-Gb/s pseudo-random binary sequence and jitter of 10-GHz signals with sub-picosecond resolution while consuming 1:9 mW from a 1-V supply. A high-resolution radix< 2 pipeline time-to-digital converter (TDC) is also proposed as a candidate for on-chip jitter measurement. The TDC employs a novel time-difference amplifier which has a large input range and less sensitivity to process variations and mismatch. The simulation results in a 0:13-um CMOS technology show that the TDC has 0:58 ps resolution with 1:6 ns input range while consuming 16:8 mW from a 1:2-V supply.