The Design Of High Accuracy On-Chip Jitter Measurement Circuit

The key performance metric for clocks is often stated in terms of jitter, which reflects the spectrum purity.cycle stability and phase offset of clock. Therefore, clock jitter testing is an important step to ensure reliable operation of the chip. The traditional jitter testing is mainly dependent on the expensive external automatic test equipment, which increases test cost, introduces test noise and reduces test precision. To solve these problems, the on-chip jitter measurement technology based on built-in self-test technology becomes a research highlight.Through the research of different on-chip jitter measurement methods,a high accuracy jitter measurement circuit based on undersampling method is designed to overcome the existingshortcoming, including the low sampling efficiency, the low jitter extraction algorithm accuracy and the high data processing method error.This scheme is made of multiphase sampling technology, mean-edge aligned jitter extraction technology and single-edge accumulation data processing method. Multi-phase sampling technology achieves the parallel sampling based on the specially designed multi-phase clock generation circuit. The mean-edge aligned jitter extraction technology replaces the median-edge alignment with mean-edge alignment, which filters low-frequency noise component to extract the jitter. Single-edge accumulation data processing method accumulates one edge in each cycle, blocking the correlation of adjacent sampling location to improve measurement accuracy and save the area overhead.A behavior level model of the proposed technology is built in MATLAB toverify the circuit function. Experiment results show that the proposed method has high measurement accuracy and wide measurement range. Then the presentedcircuit is fabricated on the SMIC 40nm LL technology by standard digital circuit design flow. The entire design area is 90.2×101.6?m2.Post-layout simulation shows that the proposed jitter measurement circuit detect the on-chip jitter less than5% error.At last, the measurement error is 10.64% through the DE2-115 FPGA board of Altera.