The Study Of PLL Chip Test And Testboard Development

Phase Locked Loop(PLL) as a clock chip, is widely used in wireless communication and other electronic devices. The major functions of PLL include phase synchronization and clock synthesis. O ne of the key parameters ind icating the chip performance is jitter characteristics. How to assess the jitter characteristics of a PLL has been a top issue with growing importance. It’s far from enough to simply rely on front-end simulation or back-end simulation given that software s imulation can merely reflect the correctness of the IC logic design or of the structure selection, however concerning the true environmental variables and the taping-out errors, software is incapable of emulating such effects. Therefore we must implement function verification and reliability verification based on entity chip test so that we can eventualy assert the PLL design is of great performance or not.This article will discuss the fundamental theory of PLL C hip Test and analysis of jitter factors. The main contents of this article are listed as follows.(1) Briefly introduce the working principle of PLL chip, phase nosie analysis and jitter simulation etc.(2) PLL chip test, applying oscilloscope, phase noise meter, testboard and data analysis software etc. to measure the various PLL parameters such as frequency, amplitude, period jitter, histogram, and eye diagram, is an efficient method to validate the PLL properties.(3) Focus on jitter causes determination, jitter categorization as well as jitter decomposition measurement. Via controlled experiments and repeated experiments, this article researched deeply in jitter sources locating and then proposed low input error test methods.(4) This article is committed to the study of PLL chip test approach and jitter factor determination. And in order to precisely evaluate the jitter charateristics it draws much emphasis on PLL testboard development, including schematics design, PCB design and devices selection.In summary, PLL Chip Test, as a feedback to the logic design stage can orienate the designers to modify or optimize the IC design. PLL test which cooperates with PLL IC design to achieve highly advanced perfomance, bears tremendous significance.