Low-power Complex Logic Gate Design

With the development of the CMOS integrated circuit, the increasing of the working frequency and the integrated density of IC leads the power consumption becomes the bottleneck in VLSI circuit design. During the IC design, the complex logic function of IC can be realized by calling the basic function units(gates). But research shows when some logic functions produced by the combination of basic gates replaced by complex gates which are designed on purpose using transistors, the performance of ICs can be improved such as area, delay, power and so on. This thesis focuses on the low-power complex gate design, and the analysis of the performance of the complex gates under different working condition. The thesis mainly consists of the following three sections:1. The research of the complex gate design of Traditional Boolean(TB) logic. Against the traditional Boolean logic design which employs has only used the some based basic cell circuits such as AND/NOT, NOT and OR/NOT, etc., to realize large-scale logic circuit complex logic functions. Through such circuit design methods are easy to access cells, but it usually needs more transistors and which leads the circuit area increasing. Compared to the complex logic gates of TB logic by which realized using the basic TB logic gates in cascade structure, transistor-level complex logic circuit gates have a smaller area and lower power consumption.2. Design and analysis of performance of the complex gate using Reed-Muller(RM) logic. Comparing to existing RM logic, such as three-input OR/XNOR, XOR/AND, used in the form of a two-input cascade structure, which leads to higher power consumption and longer delays, a transistor-level design of complex logic structures is proposed in this thesis. A multi-rails structure and hybrid-CMOS logic style are taken and the signal transmission path is shortened in the proposed circuit. Compare to the published complex gates which use single-rail, the performance of the proposed circuit is improved in power and delay. Under the 55-nm CMOS technology and PTM technologies,HSPICE and Cadence post-simulation show that the proposed circuit has correct operation and greatly improved in delay, power and power delay product(PDP) under the various loads, input frequencies and PVT combinations.3. The test environment and the performance measurement methods. The environment and the measurement are very important issues in the performance test. To compare the performance of circuits, the test methods given by designers often cannot fully measure the performance of circuits. By studying and comparing the ways of the measurement of the circuits’ performance, a comprehensive way is presented and used for the performance test in this thesis.