| This, thesis is devoted to efficient VLSI architecture design issues in error control coders, including overlapped sum-product (SP) Low-Density Parity-Check (LDPC) code decoding algorithm, Reed-Solomon (RS) based LDPC code decoder, Quasi-cyclic (QC) LDPC coded multi-band orthogonal frequency division multiplexing (MB-OFDM) ultra wideband (UWB) system, and multi-rate LDPC code decoders.; In time-multiplexed LDPC decoder architectures, to obtain a higher throughput by reducing clock cycles required per iteration, overlapped decoding algorithm is proposed and it is shown that required number of clock cycles can be reduced by more than 40%.; Two types of decoder architectures are presented for RS based LDPC codes. One is oriented for low/medium throughput applications. An efficient memory address generation scheme is proposed for this architecture. The other is oriented for high throughput applications such as 10GBASE-T (10-Gigabit Ethernet Transceiver Over Copper). The architecture is developed to have low interconnection cost between storages and processing units.; Two methods are proposed to design multi-rate quasi-cyclic (QC) low-density parity-check (LDPC) codes and their capability and suitability for MB-OFDM UWB systems are examined in terms of code performance and multi-rate decoder architecture complexity. It is shown that multi-rate QC LDPC codes can be mapped to low-cost decoder architectures. |
