High Efficient LDPC Deocder Design For HINOC 2.0 System

This thesis proposes a high speed Low Density Parity Check?LDPC?decoder for High-performance Network Over Coax?HINOC?2.0 systems.Compared to its predecessor HINOC 1.0,HINOC 2.0 systems enhance the requirements in all aspects,especially in the LDPC decoding performance,and thus bringing huge challenge to design of LDPC decoder.First of all,lower error floor?1×0?^-12)leads to complexity of LDPC codes construction,and requires decoder to support higher number of iterations.Next,higher throughput?1Gbps?demands high efficiency of iterative decoding and small circuit latency of LDPC decoder when processing massively parallel data flows.Finally,hardware resource cost should be reduced as much as possible when satisfying the above requirements.Firstly,in order to fulfill the lower error floor,this thesis proposes an advanced Ping-Pong RAM based parallel architecture.It adopts advanced Ping-Pong RAM to store massively parallel LLR?log-likelihood ratio?flows,and prolongs the total time for iterations of each decoder core by 4times,within reasonable hardware resource cost.As a result,the number of iterations supported are increased,which enhances the error correction performance.Furthermore,an auto additional iteration scheme is designed by exploiting the characteristics of HINOC 2.0 systems.It enables the proposed decoder to adjust the number of iterations dynamically according to the time intervals of input LLRs,and therefore the number of iterations is maximized,further promoting decoding performance.Secondly,in order to achieve the higher throughput,a pipelining high speed full parallel decoder structure is designed.It takes full use of parallelism of adopted codes,and multiplex the check node/variable node processing unit?CNU/VNU?.The critical path of CNU/VNU is also optimized for increasing the maximum working frequency.The proposed pipelining full parallel structure enhances the efficiency of decoder core and resource utilization.With the rearrangement of sub-matrix RAM by the principle of merging those RAMs with the same address control logic,the hardware routing complexity is efficiently reduced.Thirdly,in order to reduce the total hardware resource cost,this thesis proposes a data sequence exchange mechanism.Through simple exchanging of data sequence,the data hazard problems encountered in high-speed parallel scenarios are solved,so that the proposed decoder enables to store parallel input data?16 LLRs?in very short time?1 clock cycle?and complete initialization in the shortest time?24 clock cycles?.The proposed data sequence exchange mechanism saves the hardware resource efficiently.Finally,The proposed LDPC decoder is implemented on Stratix V5SGXEABN3F45C3.According to on-board test result,proposed LDPC decoder achieves high throughput of 2.1 Gbps with maximum working frequency of 145MHz.The error floor is proved to be lower than 1×0)^-12.In a conclusion,the proposed LDPC decoder can fulfill the high requirements of HINOC 2.0 systems.