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A High Rate Ldpc Code Encoding And Decoding Algorithm Realization

Posted on:2009-02-04Degree:MasterType:Thesis
Country:ChinaCandidate:X Y XiangFull Text:PDF
GTID:2208360245461003Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Low-Density Parity-Check (LDPC) Code is invented by Gallager nearly 40 years ago and has been rediscovered and generalized recent years. This kind of error correcting code can achieve near Shannon limit error performance and represent a very promising prospect for channel error coding. LDPC code is widely considered as next-generation error-correcting code for telecommunication and magnetic storage. The decoding algorithm and its implementation design of a special subclass LDPC code are the foucs research area of this dissertation.Regular belief propagation (BP) algorithm, or sum-product algorithm, can achieve good decode performance by iterative message processing between message and check nodes. But due to its high compute complexity, there come out several simplified decode algorithms such as BP-based algorithm, a posteriori probability (APP) based algorithm. They reduce decode complexity by simplifying the process in either bit nodes or check nodes at the expense of performance degradation. However, by improving the BP-based and App-based algorithms by normalization; it can achieve better error performance while increase little decoding complexity.This paper introduces a class of high rate LDPC code, and then compares decoding complexities and performances of different decode algorithms, according to the results, one algorithm with good performance and less complexity is chosen. After the discussion of the architectures of the hardware implementation of LDPC decoder, the partly parallel architecture is suitable for realization .To demonstrate this joint design methodology, a FPGA implementation of code length 529, code rate 0.87 regular LDPC code is realized. Every module of the decoder is introduced in chapter four, the whole design is described in the Verilog hardware description language (HDL) with maximum 10 decoding iterations; and the work clock of the decoder is 20MHz.Besides, according to the special structure of this subclass of LDPC code, this article presented an effective encode algorithm, it can make the linear complexity of encode process possible.
Keywords/Search Tags:LDPC Codes, Belief Propagation, Partly parallel architecture, FPGA
PDF Full Text Request
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