Multi-rate LDPC Decoder Based On Stochastic Computation

The LCPC is one type of the linear block codes, which has sparse parity checkmatrix. LDPC was reintroduced in the1990s and show the excellent performance whichclose to the Shannon limitation. Thus, the LDPC quickly became one of the hot researchareas in academic and industry fields. A lot of research results have be achieved. LDPCis adopted as the channel coding scheme for several standards, including DVB_S2,CMMB, WiMAX (IEEE802.16e) and10G Ethernet (IEEE802.3an).The decoding algorithm is an important issue for LDCP research recently. WhenGallager first proposed the LDPC codes in1962, the decoding algorithm did not drawnthe world’s attention for a very long period of time because of the high hardwarecomplexity. With the development of VLSI technology and decoding algorithm, theLDPC decoder eventually can be implemented in hardware and attract people’sattention to its superior performance.The focus of this study is the decoding algorithmof the LDPC with stochastic computation method, which has advantages of fastdecoding speed, simple hardware structure. Thus, the parallel architecture can beachieved efficiently. In this paper, we achieve multi-rate LDPC decoding module basedon stochastic computation method. The main work and innovations of this thesis arelisted as following:1. We construct a parity check matrix consists of three different bit rate. The hardwarestructure of the decoder is defined by the maximum bit rate. The multiple rate decodingcan be achieved by hardware configuration. So it’s convenient to choose the mostsuitable rate according to the SNR of the channel.2. We apply Half-Broadcasting technology in decoder architecure design to reduce thecomplexity of the connection between the check nodes and variable nodes. Thus, criticalpath of the hardware structure with this technology can also be reduced to improve thethroughput of the system.3. According to the performance degradation cuased by the check node degree withhigh bite rates，we change the connection structure at the output of the check node andthe way of information transmision to achieve high performance. This method also can reduce the hardware at the check nodes and the error bit spreading among the nodes。4. After establishing the hardware and software system，we use simulation toanalysis and verify the decoding performance. We realize the decoder with FPGAplatfrom, Xilinx VCX6-550T.