A High-Performance Audio ∑△ ADC In 65nm CMOS Process

The growing huge market demand of digital audio/video technology in recent years has promoted the research and development of audio ADC in China, especially high-performance audio ADC. With the advantages of its insensitivity to component precision in CMOS integrated circuit,ΣΔADC has become the main way to achieve high-precision audio ADC and it's very suitable for digital audio applications.In this context, a 18 bits high-precision low-power audioΣΔADC was designed and implemented, from system modeling design, analog circuit design, digital RTL code programme, layout design, to the chip test.The main work and innovations include:1,The basic principle of EA ADC was introduced systematically. By the discussing and comparison of various architectures ofΣΔADC, a 2-1 cascaded modulator topology with one bit quantizer and 128 OSR is adopted in this system design. Then a high-performance audioΣΔADC was designed considering various non-ideal factors.2,A two-stage telescopic OTA is adopted for its high voltage gain, low power dissipation and low noise most important. Benefit from the OTA's large output swing, integrators could use power supply and ground as feedback voltage references, which not only enlarged input range of the modulator to rail-to-rail, but also greatly reduced the power dissipation. What's more, the area cost also decreased. 3,a low-power, area-efficient digital decimation filter was designed using RAM and ROM. Compared to DFF storage strategy, half of the hardware cost could be saved using this method.4,A digital correction module used to reduce the offset error and gain error was designed to improve the dynamic range of theΣΔADC system. The errors were firstly sampled to the memory, then the data could be corrected by subtract these samples.5,A serial peripheral interface was introduced, by which theΣΔADC could communicate with MCU. With the full-duplex communication, I/O pins could be retrenched, saving a good deal of area, especially at 65nm or even small process, where PAD became a major consumption of the chip area.6,The chip has been implemented in SMIC 65 nm Mixed-Signal 1P8M CMOS standard silicon process.The chip area is 0.6 mm2. Experiment results shew that,89 dB SNDR and 93 dB DR were achieved for audio bandwidth. The power dissipation is 2.2 mW under 1.2 V power supply. Besides, the prototype yield is more than 90%.7,The design improvements are performed after chip tests including a programmable gain operational amplifier for industrial applications.