Dynamic CMOS circuit power dissipation methodology in low power high bandwidth chip design

In a Power Efficiency System (PES), Energy Efficiency Systems (EES)/Energy Aware Computing (EAC) is a qualitative system attribute that is quantified through specific measure at the same time. In this dissertation, low power dynamic CMOS circuit for a power dissipation methodology will be considered as a high bandwidth communication chip design. Dynamic CMOS high performance chips and system design in Hierarchical Power Efficiency System (HPES) will be considered for high bandwidth communications while low power consumption and high speed are major design goals in VLSI design area.; In order to improve the power vs. bandwidth tradeoff, it is necessary to consider digital power dissipation methodology and power reduction techniques. Based on experiments, we are maximizing the performance of chip taking into account delay and power. This dissertation describes the behavior of power dissipation tradeoff between performance and energy with dynamic and static power consumption in low power high bandwidth CMOS circuits. It also discusses a novel approach of Dynamic Multi-Threshold (DMT) logic in static power consumption. The results of computer simulations of these circuits are compared and possible improvements and applications are discussed.