Design Of Low Power Dissipation Class D Audio Power Amplifier Subsystem

In this paper, a low power consumption class D audio amplifier is designed. This design is main used in portable audio device. It have following characteristics. First, a I2C compatible interface circuit has been design to make this chip can be controlled by CPU or MCU. Second, a new PWM modulation technology is get in used. At last, the circuit structure has been simplify to make the chip have smaller dimension.Compared with traditional class AB amplifiers, the class D audio amplifiers have more efficiency. So, in portable audio devices which are more and more popularity, using the class D audio amplifier can make the battery more durable than before. Otherwise, because it's high efficiency, the temperature above chip will not very high, we can use smaller Package scheme, this will help to the miniaturization of portable device. Now the research on class D amplifier is weak in our country, the research in it will help to the popularization of our own class D audio amplifier.After analyze on class D's structure and factors which influence on class D's efficiency. A circuit has been design. This circuit use fully differential form, integrator integrate fully differential signal, this will distinctly reduce noise and RF interference come from power mos, at the same time, the BYPASS capacitance which is used to increase the stabilization of reference voltage is been cancelled. It also have a triangular generator in itself, the PLL circuit and external capacitance, the new filterless PWM modulation saved the filter capacitance, greatly reduce the application area on PCB.This project use Cadence Spectre to do circuit simulation, Cadence Virtuoso to do layout design. The result show every module can achieve design requirement, this circuit can work properly under supply voltage of 2.5V to 5.5V, when supply voltage is 5V and load is 4Ω, the highest output power is 2.5W, high efficiency can also be guaranteed, when load is 8Ωand output power is 1.75W, efficiency is up to 75.1%. When work properly, quiescent current is 3mA and shutdown current is 0.5mA, so it have low quiescent power dissipation. The output low pass filter can be omit due to the PWM modulation of new generation, so the area spend on PCB board will be saved. A innovative fully differential integrator is designed, in which differential signal is integrated, as a result, the cap for stability on bypass can be saved, so as the layout area and cost for production. This chip use the CSMC 0.5μm DPTM mixed signal standard CMOS process for production, 4×4mm~2 TSSOP-16 for packaging. Now it has successful MPWed and the test shows it has good performance.