Design Of Low-leakage Power CMOS Standard Cells In Nano-meter Technology

With the rapid progress of integrated circuits, very large scale integration(VLSI) design process has entered the nanoscale. The scaling MOS threshold voltage results in the leakage current of chip increased exponentially, so that leakage power becomes more and more significant in power consumption of nanoscale CMOS circuits.Standard cells play an important role in digital integrated circuits design. In nanoscale CMOS circuits, reducing leakage power consumption of standard cells will directly lead to the leakage power of ASIC chips decreased. Therefore, the low leakage power of standard cells research is significant for the ASIC chips low leakage power design.The background of standard cells library building technology and the leakage power reduction techniques are described in this paper. The low-leakage standard cells technology is studied in NCSU 45 nm process. Then we build a low-leakage power standard cells package in this paper to support the low-leakage power ASIC design with the standard cells package.The main research work of this paper can be divided into several parts as follows:1. Low-leakage power reduction techniques are discussed, and applied them into the design of standard cells’ package. We reduce the leakage power of the standard cells including combinational gate cells and flip-flops by using gate-length biasing technique in NCSU 45 nm process; besides, we propose a new low-leakage autonomous data retention master-slave D flipflop with power gating technique.2. The layouts of low-leakage standard cells are drawn by Virtuoso IC610, and they meet the rules of NCSU 45nm’s lib. We get the layout file(GDS file) of low-leakage standard cells package by Stream Out. All low-leakage power cells’ layouts are drawn in strict accordance with the rules from NCSU 45 nm design process to reduce errors when place and routing using low-leakage power cells. The height of all the standard cells is the same, and the PIN should be placed at the intersection of the horizontal and vertical routing lines to insure that the layouts are easy matching when place and routing.3. The physical and timing synthesis libraries of low-leakage power standard cells package are completed. We get the physical library by Abstract and use Liberty NCX and Hspice to characterize the low-leakage standard cells package.4. We design a 4-bit serial adder and a 16-bit FIR filter to verify the usability and effectiveness of low-leakage power CMOS standard cells package. The results show that the lowleakage power CMOS standard cells package can be used by the EDA tools. Besides, compared with using the NCSU 45 nm standard cells library, the leakage power of 4-bit serial adder and 16-bit FIR filter is reduced 9.50% and 16.77%, respectively. Otherwise, the area of 16-bit FIR filter is reduced 3.27% by using the low-leakage power CMOS standard cells package.