Low Power Design Of Reconfigurable TPM SOC With Standard Library Of 28 Nm CMOS

With the advent of the era of Internet of Everything,the information security of mobile electronic products has attracted great attention.The high-efficiency,high-security,reconfigurable Trusted Platform Module can effectively protect device terminals and prevent unauthorized users from accessing them.And power consumption is the key to mobile electronics.Therefore,research on low power design for reconfigurable TPM chips has important practical significance.This paper first describes the power consumption of CMOS,and designs a power management unit to manage the clock network in multi-levels,thereby reducing the dynamic power consumption;Secondly,based on the IEEE 1801 UPF standard,a power management system is designed to manage the working mode of the chip,thereby reducing standby power consumption;Finally,in order to optimize the overall performance of the chip,analyzes its timing path,and uses higher voltage and lower threshold cells in critical timing paths to ensure its operating speed,reduces operating voltage and uses high threshold cells in non-critical timing paths to further reduce power consumption.The main technical achievements of this paper are reflected in the following points:(1)Based on the principle of clock gating technology to reduce the activities of clock network,a power management unit is designed for the reconfigurable TPM chip.A multi-level clock management system is proposed,which can parameterize the configuration register to control the working mode of the clock network.The average dynamic power consumption dropped by 28.5%.(2)Integrates multi-levels clock management technology and power management unit to optimize the design of a dedicated power management system.According to the application scenario,the chip working mode can be flexibly selected.When the TPM encryption and decryption algorithms are not working,the power supply and the system maim clock are turned off,so that the average leakage power consumption is reduced by 18.2%,and the average dynamic power consumption is reduced by 91.6%.(3)According to the performance characteristics of each part of the chip,based on the clock management and power management system,multi-voltage technology and multi-threshold voltage technology are used to ensure that the overall performance of the chip does not decrease,and the average dynamic power consumption of 11.74%and average leakage power consumption of 73.92%are further reduced.Finally,based on the TSMC 28 nm process,a low-power layout is designed,and voltage drop analysis,formal verification,and DRC/LVS verification are performed to ensure the correctness of the design.