| Advances in VLSI has made it possible to integrate heterogeneous modules on the same chip leading to System On Chip based designs. Network-on-Chip (NoC) has been suggested as the communication resource to overcome the on-chip physical interconnect issues for complex System-on-Chips (SoCs). Present and future NoC based SoCs are designed using preexisting components such as CPUs, DSPs, memories, which we call Cores. The SoC concept facilitates the reuse of IP cores in a plug and play manner. This research proposes a novel architecture in which most of the interfacing functionality is incorporated in the generic part of the interface.; Several applications types (networking, computer graphics and multimedia applications) require a large memory space. Memory issues play an important role in the design of application-specific systems. In an SoC, there arises the problem of providing a large memory space to provide memory to all cores interface on the SoC. This thesis provides a novel Memory Organization and Packing style to ensure that the Memory Core that is interfaced on an NoC based SoC is used to its maximum capacity, without any wastage of Memory space.; For different applications e.g. Video, Communication, Computing etc., IP Cores will have different memory requirements in the same SoC design. SoC designs give the flexibility to interface an IP Core with a non-standard data width size. An architectural interface between a Memory Core and the underlying network interface to abstract varying data width sizes of different IP Cores is also presented here. In this way, IP Cores of varying aspect ratio and memory requirements, can use a single Memory Core on the SoC. |
