Design and Implementation of an Architecture for Securing On-Chip Memory in SoC-FPGA

State-of-the-art system-on-chip (SoC) field-programmable gate arrays (FPGAs) integrate hard powerful ARM processor cores and the reconfigurable logic fabric on a single chip in addition to many commonly needed high-performance and high-bandwidth peripherals. With increase in complexity of designs, they are broken down into smaller units called Intellectual Properties to promote ease of design and reusability. The increasing reliance on untrustworthy third-party IP (3PIP) cores for both hardware and software applications in embedded systems has made them increasingly vulnerable to security attacks. Detection of trojans in 3PIPs is extremely difficult to current static detection methods since there is no golden reference model for 3PIPs. Moreover, many FPGA-based embedded systems do not have the support of security services typically found in operating systems. This thesis presents a runtime memory protection architecture for on-chip memory and discusses architectural changes to optimize for low hardware cost and low-latency. The proposed architecture is designed to restrict access or enforce policy on memory transactions in a shared environment. In addition virtual addressing and encryption of data help protect confidentiality of data in case of a failure of the memory protection unit. The design is capable of Malware detection by tracking multiple illegal transaction attempts, and disabling the IP from accessing memory without the need for a reconfiguration. A survey of practical many-to-many networks was considered to find the optimal replacement for the unscalable crossbar switch. Encryption ciphers and encryption networks were implemented to improve the security of the system, while making necessary trade-offs. The design is implemented on the Intel (Altera) DE1-SoC board featuring a SoC-FPGA that integrates a dual-core ARM processor with reconfigurable logic and hundreds of on-chip memory blocks. The architecture was further extended to protect execution memories in software IPs by programming the ARM processor to provide isolation between both the ARM cores. This isolation was achieved by running the memory protection driver software and; Software IPs with its scheduler on two separate cores, with isolated memories. The experimental results and case studies show that the memory protection model is successful in preventing unauthorized accesses from malicious IPs, eliminating malicious IPs from the system without need for reconfiguration of the FPGA and arbitrating access from trusted IPs with a low area and latency overhead.