A Delta-Sigma frequency discriminator with fractional-N divider and 3-bit quantizer

The design and implementation of a new Frequency Discriminator (FD) architecture is presented in this thesis. This architecture has finer frequency resolution and lower frequency noise compared to existing architectures. This superior performance is achieved by incorporating a fractional-N divider and a multi-bit quantizer. The new architecture is based on Delta-Sigma (DeltaSigma) Modulation techniques and converts instantaneous frequency directly to digital form.; Simulation models were developed in Matlab Simulink to explore the effect of various parameters on performance. The models then were transformed into circuit blocks. The circuit blocks were simulated both at the behavioural and the transistor level. The design was fabricated in 0.18 mum TSMC CMOS process.; This FD architecture is suitable for use in high resolution frequency synthesis and frequency demodulation applications.