Finite impluse response current steering radio frequency digital to analog converter for digital-IF transmitter architecture

The demand for high-data rate multi-media wireless connectivity puts stringent requirements on the transceivers in terms of die area, power consumption, linearity, efficiency and noise. Super Heterodyne and direct conversion architectures are widely used in wireless transmitters; they each have their advantages and limitations. Digital intermediate frequency (IF) transmitters combine advantages of homodyne and heterodyne transmitters in architecture suitable for integration with digital complementary metal oxide semiconductor (CMOS) and software defined radio.; This work focuses on the idea of direct digital to radio frequency (RF) converters to be used in digital-IF transmitters. The idea is demonstrated by simulations and measurement results from two RF digital to analog converter (DAC) designed and implemented on silicon, the first one on a 0.25 mum CMOS and second on a 0.18. mum CMOS.; The first architecture is a noise-shaped direct digital IF to RF DAC with embedded upconverter mixer. The digital IF signal is noise shaped by a band-pass sigma delta modulator with single bit IF output followed by a semi-digital finite impulse response (FIR) filter. The current mode FIR filter combines scaled values of the LO signal for performing reconstruction filtering and upconversion in a single cell. The embedded DAC Mixer RF upconverter modulates the digital IF signal with a digital LO signal. This topology eliminates the transconductance nonlinearity of conventional mixers and is inherently linear. Presented architecture reduces clock jitter sensitivity of single bit DACs by masking IF clock transitions with LO signal. A prototype of the digital intermediate frequency to radio frequency (DIF2RF) DAC is designed and fabricated in a 5-layer metal 0.25 mum digital CMOS process. The architecture can be used in low-power software defined digital-IF transmitters. The second architecture utilizes the idea of RFDAC in a practical implementation suitable for industry standards of WCDMA and WLAN. The DAC has a 40-tap semi-digital embedded FIR filter to suppress the quantization noise of the 1/4 sigma delta modulator below spectral emission mask of the aforementioned wireless standards. A doubly-balanced mixer upconverts the DAC current to RF. The RFDAC is followed by a VGA that implements the WCDMA required dynamic range.