Memory module for network on chip architecture

Advances in VLSI design techniques have made large complex Systems on a Chip (SoC) a reality. The complexity and size of these SoCs calls for review and revision of on-chip communication techniques. In an attempt to address this problem of connecting heterogeneous intellectual property (IP) cores on the same chip, Network on Chip (NoC) has been suggested as a communication framework. A number of architectures have been proposed for NoCs which connect reusable IP blocks on a communication framework. However a generic interface which can be used for various architectures and cores with minimum redesign in the IP has not yet been developed. We have implemented a generic network interface and a global memory which can be accessed by multiple cores on the NoC. We have also designed a finely-pipelined reconfigurable memory which can be plugged on the NoC via a network interface. We have compared its performance with a stand-alone computing unit on the network and found that the reconfigurable memory architecture has better performance and lower bandwidth requirements.