Design Of Multi-level Network-on-Chip(NoC) With Memory Protect Unit

With the rapid development of intergrated circuit technology and the strong push from application requirement, microprocessor evolves from time-shared bus-based single-core/multi-core architectures to parallel-processing network-based multi-core architectures. On multi-core processors, as the number of processor cores, memories, and peripherals increases, the amount of on-chip data communication rises up dramatically, and the data protection problem of shared memories becomes serious. Therefore, it is urgent to study on designing high efficient Network-on-Chip and memory protection mechanism.The paper proposes a multi-level Network-on-Chip with memory protection units, named Express Net, for our self-designed homogenous microprocessors with eight DSP cores called Octa-Core DSP. The proposed Express Net can meet the communication demands of Octa-Core DSP and have the features of high bandwidth and low latency. Besides, it also provides security of on-chip data access of Octa-Core DSP. The main work and contributions is as follows:The development and research status of Network-on-Chip and memory protection are analyzed. Then, by considering the architecture characteristics of Octa-Core DSP, the overall structure of the multi-level Network-on-Chip with memory protection unit, Express Net, is proposed.The multi-level Network-on-Chip is designed and implemented: Firstly, the performance requirements of multi-level Network-on-Chip are analyzed; Secondly, its overall topological structure and the topological structures of each level are designed. Thirdly, flow control mechanism, strategy of arbitration and distribution, crossbar, routing table and parameter registers are designed in detail. Finally, based on AMBA AXI4 protocol, the network protocol of the multi-level Network-on-Chip is designed.The memory protect unit is designed and implemented: Firstly, the needs of the memory procteion functions on Octa-Core DSP are analyzed.Secondly, the overall structure of the memory protect unit and its position in the multi-level Network-on-Chip are planned.Thirdly, each function of the memory protection unit is designed in detail, including authority level, permission structure, access control flow, parameter registers, etc.The ExpressNet are validated: Firstly, the verificaition strategy is planned detailedly according to the current verification methodology. Secondly, model-level verification of the multi-level Network-on-Chip and the memory protection unit are carried out respectively, and the results are analyzed and discussed. Finally, the entire simulation platform of the multi-levelNetwork-on-Chip with the memory protection unit is built up. Functions are verified and results are analyzed.