Methods For Enhancing The ATPG Efficiency Of Dynamic Current Testing And At-Speed Current Testing Simulation

Integrated Circuit (IC) testing is critical for high quality ICs and high yield of IC production. Testing based on stuck-at fault model is insufficient for high performance ICs, especially for CMOS circuits. Quiescent power supply current (I_DDQ) testing has become an accepted test method by the IC industry since the idea was proposed in early 1980's.Using IDDQ testing can reduce the cost of testing and enhance the reliability of the chip remarkably. However, some defects, such as some stuck-open defects in CMOS ICs still cannot be detected by Iddq testing or by logic testing, and at the same time it faced some challenges of increasing leak electric current in deep submicro technology. Due to these limitations, in order to improve the fault coverage of the testing to meet the demands of people, the dynamic current (I_DDT) testing was proposed to detect some faults that cannot be detected by other testing methods.It takes too much of time in total to generate a test pattern for each fault, and which is not necessary since a certain relation exists between the troubles of circuit, such as relation of "equivalence" and relation of "domination", which can be detected by the same test pattern. This paper focuses on how to reduce the number of stuck-open faults detected by dynamic current test technique for enhancing the auto test pattern generation (ATPG) efficiency. This can be done in the way that nearer the site of a fault to the primary outputs of the circuit under test, earlier the auto test pattern generation (ATPG) for this fault starts, and adjust the control cost parameter dynamically and reverse the order of test pattern. With the premise of keeping "robust" of the original algorithm, using this method can reduce the number of the faults and enhance the time efficiency of ATPG obviously. Experimental results show that about 70% of ATPG time is cut down.In addition, in order to verify the efficiency of ATPG, a waveform simulator has been modified, which can make it to detect faults when gate delays are assigned in the range of 10% of their nominal values. The gate delays which were used satisfied normal distribution. Experimental results proved that the ATPG algorithm is effective.Finally, in order to verify the feasibility of at-speed current testing, by using PSPICE software, some faults were been simulated for C432, which included open fault, stuck fault and redundant fault. It shows that the distinction between fault free circuit and faulty circuit is large, which fully proved that the application of at-speedCurrent testing in the industry is feasible.