Transient Current Test Generation And Fault Simulation

Voltage Testing and Current Testing are both applicable to testing of digital circuits. Voltage testing have been well developed and widely used in practice. Current testing can be adopted as a supplementary method to increase reliability of ICs. The transient power supply current (IDDT) testing can detect some faults undetectable by any other test method, and increase fault coverage.Based on the analysis and research on FAN algorithm, an IDDT test pattern generation algorithm for stuck-open faults is present. In the case of ignoring hazards, for the stuck-open faults in CMOS circuits, the feasibility of transient current test generation based on FAN algorithm is discussed. Three different D-fronts are defined in this paper, and the test generation is consisted of three parts: to excite the fault at first; to maximize the IDDT difference between fault-free circuit and faulty circuit at second; and finally to minimize the effect of bypass.Due to the subtle error among different manufacturing equipment, the gate delay of circuits is different and varies in a given scope, which induces the time uncertainty of the waveform. A 4-tuple (v,f, h1, h0) is used to express the waveform of a signal line l in a period. The output tuple calculating method for all elementary gates is given. The stuck-open faults are simulated concurrently based on IDDT testing with the test pattern pairs generated above. The feasibility and effectiveness of the IDDT testing are both validated by experiments. At last, Transistor bridging faults are simulated based on IDDQ testing and gate bridging faults and stuck-at faults based on voltage testing through detaching a pattern pair into two independent patterns.