Dynamic Current-based Ic Testing

As modern technology allows dramatically increasing complexity of integrated circuits, the impacts of the defects in transistors on the circuits, which can not always be detected by traditional test methods, are growing. So, the testing methods are tasked to keep pace with the phenomenal growth. In this dissertation, the VLSI (very large scale integration) test method based on IDDT (transient current) information, a new hot spot of test strategies, is researched.First of all, the background and current situation of this research are brought forth..Secondly, a model, based on directed graph, for circuit tested by IDDT test method is proposed. And further provide an algorithm of test vectors generation and IDDT path searching. All of the IDDT paths corresponding to any test vector can be got through this algorithm. And the fault can be located in transistor lever or path level. At the same time, as more and more IC designed using standard units, an algorithm of test vectors generation and IDDT path searching is presented based on standard units. Any IDDT paths mapping some test vector can be searched out, and the minimum number of test vectors aiming at a certain target to reduce the test time consumption can be selected before testing executed through this algorithm. Correctness and efficiency of this method are demonstrated through programme.Correlation Analysis Approach is studied, aiming at the complicated faults that are difficult to be detected through voltage and IDDQ testing method, such as bridge fault and resistive-open fault. In this paper, the Correlation Analysis Approach is introduced into the extraction of fault features from IDDT information for the first time. In Correlation Analysis Approach, sub-band filtering the IDDT is achieved with a filter bank implemented by Cosine modulation and wavelet. Correlation coefficient and coherence function of the sub-band response sequence is calculated. Then the diagnosis of fault is carried out taking the correlation coefficient and integral of coherence function sequence as the fault features. The simulation results and the data analysis of the experimental circuits demonstrate that this method is effective for the faults that can not be detected by voltage and IDDQ testing. Finally, the summary and the improving direction of the algorithms and methods are introduced.