| Digital systems design is changing rapidly as integrated circuit technology evolves. The arrival of deep submicron technology brings about increasing design challenges in terms of obtaining circuit reliability, increasing need for low-power design, and the handling of system complexity. It is critical to cope with these challenges in both circuit design and in automated computer-aided design (CAD) flows.; One attractive alternative is to use robust asynchronous circuits which gracefully address some of these problems. Asynchronous circuits communicate through handshaking in a distributed way rather than by adopting a centralized control such as the global clock. Asynchronous design has been the focus of renewed interest and research activity because of its potential benefits of low power consumption, low electromagnetic interference, robustness to delay variations, and modularity of designs. However, they typically suffer from high area and latency overhead, as well as lack of CAD tools and optimization techniques. Also, careful design is required since hazard-freedom is essential for their correct operation.; This thesis presents optimization techniques for a class of asynchronous circuits, called asynchronous threshold networks, which is one of the most robust asynchronous circuit styles. Two techniques are proposed: (i) technology mapping and cell merger, and (ii) relaxation. The technology mapping and cell merger algorithm optimizes the circuits using a specific technology library while the relaxation technique relaxes the overly-restrictive style of the circuits. Both of these techniques optimize area or delay of the circuits while still fully-preserving their robustness properties. Also, the proposed algorithms were implemented in automated CAD tools, called ATN_OPT Toolset (available for free download on the web http://www.cs.columbia.edu/-nowick/asynctools). Experiments were performed on industrial circuits and largest MCNC benchmarks with significant improvement in both area and delay. |
