| Scope and method of study. The main focus of this thesis is to design a Static Random Access Memory (SRAM) Compiler that could generate memories of required configurations. The layout designs are created using Cadence Virtuoso in NCSU FreePDK45 technology process and simulated using Synopsys Nanosim.;Findings and conclusions. A high speed embedded single port SRAM compiler has been realized in NCSU FreePDK45 Process technology. The simulation results of certain configurations are given and compared. The areas are calculated along with the access times. This compiler can generate the whole SRAM array including layout, LVS netlist, verilog model, LEF file and datasheet. |
